1. Technical Field
The present invention relates generally to an improved data processing system and method. More specifically, the present invention is directed to a system and method for management of an input/output virtualization (IOV) adapter, such as a Peripheral Component Interconnect (PCI) IOV adapter, through a virtual intermediary in an IOV management partition.
2. Description of Related Art
Most modern computing devices make use of input/output (I/O) adapters and buses that utilize some version or implementation of the Peripheral Component Interconnect standard, which was originally created by Intel in the 1990s. The Peripheral Component Interconnect (PCI) standard specifies a computer bus for attaching peripheral devices to a computer motherboard. PCI Express, or PCIe, is an implementation of the PCI computer bus that uses existing PCI programming concepts, but bases the computer bus on a completely different and much faster serial physical-layer communications protocol. The physical layer consists, not of a bi-directional bus which can be shared among a plurality of devices, but of single uni-directional links, which are connected to exactly two devices.
FIG. 1 is an exemplary diagram illustrating a system incorporating a PCI Express (PCIe) fabric topology in accordance with the PCIe specification. As shown in FIG. 1, the system 100 is comprised of a host processor (CPU) 110 and memory 120 coupled to a root complex 130, which is in turn coupled to one or more of a PCIe endpoint 140 (the term “endpoint” is used in the PCIe specification to refer to PCIe enabled I/O adapters), a PCI express to PCI bridge 150, and one or more interconnect switches 160. The root complex 130 denotes the root of an I/O hierarchy that connects the CPU/memory to the I/O adapters. The root complex 130 includes a host bridge, zero or more root complex integrated endpoints, zero or more root complex event collectors, and one or more root ports. Each root port supports a separate I/O hierarchy. The I/O hierarchies may be comprised of a root complex 130, zero or more interconnect switches 160 and/or bridges 150 (which comprise a switch or PCIe fabric), and one or more endpoints, such as endpoints 140, 170 and 182-188. For more information regarding PCI and PCIe, reference is made to the PCI and PCIe specifications available from the peripheral component interconnect special interest group (PCI-SIG) website.
In addition to the PCI and PCIe specifications, the PCI-SIG has also defined input/output virtualization (IOV) standards for defining how to design an I/O adapter (IOA) which can be shared by several logical partitions (LPARs). A LPAR is a division of a computer's processors, memory, and storage into multiple sets of resources so that each set of resources can be operated independently with its own operating system instance and applications. The number of logical partitions that can be created depends on the system's processor model and resources available. Typically, partitions are used for different purposes such as database operation, client/server operation, to separate test and production environments, or the like. Each partition can communicate with the other partitions as if the other partition is in a separate machine. In modern systems that support LPARs, some resources may be shared amongst the LPARs. As mentioned above, in the PCI and PCIe specification, one such resource that may be shared is the I/O adapter using I/O virtualization mechanisms.
While the PCI-SIG provides a standard for defining how to design an IOA which can be shared by several LPARs, this specification does not define how to connect the IOA into a host system. Moreover, the standard does not specify how to manage the shared functionality of an IOA utilizing I/O virtualization. This is because the PCI-SIG specification is concerned with setting standards for the operation of the PCIe fabric below the root complex. In other words, the PCI-SIG does not provide any definition of standards for the root complex and above because that is considered the domain of system houses. That is, each of an Intel platform, an IBM Power® platform, and a Sparc platform, for example, may have different system implementation requirements that are not set forth in the PCI-SIG standards.